1. Field of the Invention
The present invention relates to a method for forming a non-volatile memory, and more particularly to a method for forming a flash memory with an inlaid floating gate.
2. Description of the Related Art
Non-volatile semiconductor memory devices, such as EEPROM and “flash” devices, are both electrically erasable and writable (or programmable). Such devices retain data even after power is shut down. Similarly, erasable programmable logic integrated circuits (EPLD, or PLD) use non-volatile memory cells to achieve certain reprogrammable logic functions. Non-volatile memory devices and PLDs, have a limited lifetime due to the endurance related stress such devices suffer each time they go through a program-erase cycle. The endurance of such devices is its ability to withstand a given number of program-erase cycles.
A main component of a cell of a non-volatile memory device or a PLD, is a floating gate, in a field effect transistor structure, disposed over but insulated from a channel region which is disposed between a source region and a drain region in a semiconductor substrate. A control or select gate is generally disposed over the floating gate, and is insulated therefrom by a dielectric layer. Alternatively, a control “gate” can be implemented by an adjacent diffused region of the substrate that is also insulated from the floating gate. The floating gate is, therefore, surrounded by an electrically insulating dielectric.
The threshold voltage is the minimum amount of voltage that must be applied to the control gate before the transistor is turned “on” to permit conduction between its source and drain regions, and is a function of the level of charge on the floating gate. The control gate acts as a word line to enable reading or writing of a single selected cell in a two-dimensional array of cells (i.e., a non-volatile memory device or PLD).
A cell is “programmed” by applying the control gate and its source and drain regions at appropriate voltages so that electrons travel from the substrate through an intervening oxide layer (i.e., a tunnel oxide layer or a tunnel oxide) and onto the floating gate. If enough electrons are collected on the floating gate, the conductivity of the channel of the field effect transistor of the cell is changed. By measuring the conductivity of the cell, it is determined whether a binary “1” or “0” is being stored. Since the floating gate of the cell is well insulated, the cell is not volatile and retains its charge for an indefinite period without any power being applied to it.
A cell or group of cells in a non-volatile memory device or a PLD, are also “erasable.” During erasing, the control gate, the source, the substrate and the drain regions, of a cell are held at a potential that causes electrons to move back through the tunnel oxide and into the substrate, usually the source region of the substrate. This movement reverses the effect of an earlier program operation.
Reliability assurance is a costly, time consuming, difficult and important task in integrated circuit (IC) development and production. This is particularly true with non-volatile memory devices and PLDs. Such devices are subject to the usual IC failure mechanisms such as package and bonding failures, electrostatic discharge, electromigration, oxide breakdown, etc. Additionally, such devices must meet other reliability requirements. For example, they must retain data for ten years and must function normally (within specifications) after repeated program and erase operations, i.e., program-erase cycles.
It is known that charge loss from a floating gate of a cell of a non-volatile memory device or a PLD is caused, in part, by positive ions (such as sodium) which are disposed in the oxide layer surrounding the floating gate. These positive ions are free to combine with electrons collected on the floating gate. The combination of positive ions with electrons results in a net charge loss from the floating gate and weakens the data retention capability of a non-volatile memory device or a PLD.
It is also known that charge loss from a floating gate of a cell of a non-volatile memory device or a PLD can occur because of damage of the tunnel oxide. The tunnel oxide could be damaged or harmed amid various processes performed after the formation of the tunnel oxide. It is etching processes, especially the etching of the floating gate, that cause tunnel oxide damages and renders the tunnel oxide unreliable. Thus damage of the tunnel oxide induced by etching must be solved since it would further cause severe charge loss amid alternatively programming and erasing the floating gate, i.e., program-erase cycling. Furthermore, the scenario could become worse as the tunnel oxide thicknesses are further reduced, and present weak data retention capability since the tunnel oxide already lost their function.
In view of the drawbacks mentioned with the prior art process, there is a continued need to develop new and improved processes that overcome the disadvantages associated with prior art processes. The advantages of this invention are that it solves the problems mentioned above.